I am a hardware engineer with a strong background in system-on-chip and FPGA design, embedded software development, model-driven design space exploration, and computer networking. As a member of the scientific staff at the Chair of Integrated Systems at Technical University of Munich (TUM), I am about to finish my work towards a Ph.D. degree.
My research in the area of Cloud Computing, Network Function Virtualization (NFV) and Software-Defined Networking (SDN) focuses on low-latency and resource/energy-efficient packet processing in telco and data center networks. I am investigating and implementing hardware extensions integrated into the network interface card of general-purpose compute servers, which enable them to adaptively offload packet processing workloads to each other when processing resources experience short-lived overloads. This allows network operators to provision less processing resources without degrading quality-of-service. Additionally, I am investigating programmable throughput and latency measurement tools for the accurate performance evaluation of network devices and virtualized network functions. As a part of my Ph.D. project, I developed FlueNT10G, an open-source FPGA-based network tester for nanosecond-precision network traffic generation, capture and latency measurements at data rates of several tens of gigabit per second. Finally, I am working on the integration of hardware acceleration (e.g., cryptographic hashing for message authentication) into programmable network data planes such as P4.
When I'm not working, I enjoy exploring the world 🧳, hiking in the Alps 🏔, running through Munich's beautiful parks 🏃♂️, taking photos 📸, cooking (more importantly: eating) delicious meals 👨🍳 and riding my bike through the city and its surroundings 🚴♂️.